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CW 282
P. Keyngnaert, B. Demoen, B. De Sutter, K. De Bosschere
Trace-based memory layout optimization for DPSs
Abstract
DSP processors often have a complex memory architecture, as their memory space, while addressed in a continuous way, physically consists of a number of different memory banks, each with their own access constraints and access times. Therefor, data placement has a major influence on the execution speed of a DSP application. We describe a mathematical model that allows us to address the problem at hand in a formal way. The input for this model is an execution trace of the program to optimize. We also show a number of solutions for the problem, based upon the model presented. First, an optimal but slow solution using a generate and test algorithm is presented. Next, we show how this solution can be sped up with only a minor loss of optimality by applying a genetic algorithm. Finally, we present a different but very fast solution, based upon the same model but using heuristics. An example for a simple, theoretical machine shows that the latter technique is very promising. report.pdf / mailto: P. Keyngnaert
